As computers have been developed to perform a greater number of instructions at greater speeds, many types of architectures have been developed to optimize this process. For example, a reduced instruction set computer (RISC) device utilizes fewer instructions and greater parallelism in executing those instructions to ensure that computational results will be available more quickly than the results provided by more traditional data processing systems. In addition to providing increasingly parallel execution of instructions, some data processing systems implement out-of-order instruction execution to increase processor performance. Out-of-order instruction execution increases processor performance by dynamically allowing instructions dispatched with no data dependencies to execute before previous instructions in an instruction stream that have unresolved data dependencies. In some data processing systems, instructions are renamed and instruction sequencing tables, also referred to as re-order buffers, facilitate out-of-order execution by re-ordering instruction execution at instruction completion time.
Re-order buffer devices are also used to allow speculative instruction execution. Therefore, data processing systems which support speculative instruction execution can be adapted for out-of-order execution with the addition of relatively minimal hardware. A portion of this added hardware includes issue logic which is used to determine a time and order that instructions should be issued. Such issue logic can be extremely complex since the dependencies of instructions and a state of a pipeline in which the instructions are being executed must be examined to determine a time at which the instruction should issue. If the issue logic is not properly designed, such issue logic can become a critical path for the data processing system and limit the frequency of instruction execution such that performance gains which could be achieved by out-of-order issue are destroyed.
The out-of-order instruction execution implemented by many prior art systems increases processor performance by dynamically allowing instructions dispatched with no data dependencies to execute before previous instructions in the instruction stream that have unresolved data dependencies. Register file renaming, renaming selected bits of architected facilities such as floating point status and control registers (FPSCR), and instruction sequencing tables (re-order buffers) facilitate out-of-order execution by re-ordering instruction execution at instruction completion time. For more information on such structures, refer to "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," by R. M. Tomasulo, published in IBM Journal, January 1967, pp. 25-33. It should be noted that these devices are also used to allow speculative instruction execution. Therefore system architecture supporting speculative instruction execution can be adapted for out-of-order execution with the addition of relatively "little" hardware and few overhead expenses. Thus, register file renaming may support out-of-order execution without modification from a speculative instruction execution architecture. However, renaming of the floating point status and control register (FPSCR) is typically insufficient to support out-of-order instruction execution operations, even though it is utilized to perform some functions in speculative instruction execution. In prior art renaming methodologies, values were saved in rename buffers that were exact and complete for execution of an instruction. Therefore, when a data processing system was "told" to complete, the appropriate value was selected and stored in an architected destination in an unmodified state. For in-order, but speculative execution, this methodology was also executed for an FPSCR. A value stored in the FPSCR could be calculated exactly for an executing instruction. Subsequently, at completion, the value was read and a latest completing value was selected and put in the FPSCR. However, when instructions are executed out-of-order, an exact value to be stored in the FPSCR can not be guaranteed to be calculated exactly, because the FPSCR contains history of prior executing instructions. Thus, when an instruction executes out-of-order, results from earlier instructions in an instruction stream are unavailable as partial results are sometimes saved in the rename buffer. At completion time, the exact value must be constructed from all values completing and all prior completing values to produce a correct result.
Therefore, a need exists for a data processing system and method for implementing an FPSCR that may be obtained in a correct form at completion.